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| 7 28 2 advance information system basis chip with low speed fault tolerant can this document contains information on a new product under development. motorola reserves the right to change or discontinue this product without notice. simplified block diagram interrupt control programmable spi interface dual voltage regulator voltage control gnd rx tx bat fail detect vcc monitor vbat switch supply mode control reset control watchdog & oscillator wake-up inputs fault tolerant can transceiver csb miso sck mosi reset int 5v v2 v1 max 200ma max 110ma i3 max. 100ma wake-up inputs l0 l1 l2 r1 r2 vbat (+12v) v3 (switch supply) can l 5v rth rtl can h MC33389 semiconductor technical data motorola o rder number: MC33389/d rev 3.3, 15th april 02 1 2 3 5 4 6 7 8 9 10 1 2 3 3 4 4 5 6 1 1 1 1 2 2 2 2 dh suffix v1 mosi miso sck csb rstb intb rx v2 v3 rtl vbat canh canl gnd rth l2 l1 tx l0 gnd gnd gnd gnd gnd gnd gnd nc 5 6 7 8 9 20 1 1 1 1 1 2 2 1 2 automotive sbc system basis chip silicon monolithic integrated circuit v1 mosi miso sck csb rstb intb rx l2 tx v2 v3 rtl vbat canh canl gnd rth l1 l0 1 2 3 5 4 6 7 8 9 10 1 2 3 5 4 6 7 8 9 20 1 1 1 1 1 1 1 1 1 power package ordering information device and version operating temperature range package so-28 t a = -40 to 125c MC33389adw(1) pin connections MC33389cdw(2) t a = -40 to 125c so-28 case 979c hsop-20 dw suffix plastic package case 751f so-28 (1) version a: if device remains in reset greater than 100ms due to v1 undervoltage, device switches to sleep mode to minimise current consumption. wake-up configuration active. (2) version c: in v1 undervoltage condition, device remains in permanent reset state until v1 returns to nominal conditions. v1 protected by overcurrent and over temperature functions. MC33389cdh(2) t a = -40 to 125c hsop20 the MC33389 is a monolithic integrated circuit combining many functions frequently used by automotive ecus. it incorporates a low speed fault tolerant can transceiver. dual low drop voltage regulators, with respectively 100ma and 200ma current capabilities, current limitation and over temperature detection with prewarning 5v output voltage for v1 regulator three operational modes (normal, standby and sleep mode) separated from the can interface operating modes low speed 125kbaud fault tolerant can interface, compatible with mc33388 standalone physical interface v1 regulator monitoring and reset function three external high voltage wake-up inputs, associated with v3 v bat switch 100ma output current capability for v3 v bat switch allowing drive of external switches or relays low standby and sleep current consumption v bat monitoring and v bat failure detection capabilities dc operating voltage up to 27v 40v maximum transient voltage programmable software window watchog and reset wake up capabilities (can interface, local programmable cyclic wake up) interface with mcu through spi programmable interupt function
MC33389 motorola 2 MC33389 maximum ratings note 1: pulses 1, 2, 3a, 3b according to iso7637. note 2: refer to thermal management in device description section. note 3: pins 6,7,8,9,20,21,22,23 of so28wb package description symbol min typ max unit test conditions dc voltage at pin v bat v bat -0.3 27 v transient voltage at pin v bat 40 v t<500ms (load dump) dc voltage at pins canh canl -20 27 v transient voltage at pins canh canl -40 40 v 0 MC33389 motorola 7 MC33389 tx permanent dominant timer disable time t txd 0.75 4 ms busnormal mode and failure mode tx, mosi, sck, csb high level input voltage 0.7v1 v1+0.3v csb threshold for spi wake-up 2.2 v sbc in sleep mode, v1<1.5v csb filter time for spi wake-up 3 s sbc in sleep mode, v1<1v low level input voltage -0.3 0.3 v1 v high level input current on csb -100 -20 av i =4v low level input current (csb) -100 -20 av i =1v tx high level input current i tx -200 -80 -25 av i =4v tx low level input current i tx -800 -320 -100 av i =1v si, sck input current -10 10 a0 MC33389 motorola 9 MC33389 figure 1. input timing switch characteristics cyclic sense / fwu timing 3 cyt3 89.6 128 166.4 ms sleep mode (note 2) cyclic sense / fwu timing 4 cyt4 179 256 333 ms sleep mode (note 2) cyclic sense / fwu timing 5 cyt5 358 512 665 ms sleep mode (note 2) cyclic sense / fwu timing 6 cyt6 717 1024 1331 ms sleep mode (note 2) cyclic sense / fwu timing 7 cyt7 1434 2048 2662 ms sleep mode (note 2) cyclic sense / fwu timing 8 cyt8 5734 8192 10650 ms sleep mode (note 2) gnd shift detection (note 3: no over lap between two adjacent thresholds). ground shift threshold 1 (note 3) gs1 -1 -0.7 -0.3 v can transceiver active in two-wire operation ground shift threshold 2 (note 3) gs2 -1.5 -1.2 -0.8 v can transceiver active in two-wire operation ground shift threshold 3 (note 3) gs3 -2 -1.7 -1.3 v can transceiver active in two-wire operation ground shift threshold 4 (note 3) gs4 -2.6 -2.2 -1.7 v can transceiver active in two-wire operation parameter symbol min typ max unit test conditions si sclk csb don?t care don?t care don?t care val id val id t lead t wsclkh t wsclkl t r t f t lag t sisu t si(hold) MC33389 motorola 10 MC33389 device description thermal management the MC33389 is proposed in two different packages. hsop20 for high power applications and so28wb with 8 pins to the leadframe for medium power applications. hsop20 package for such a package, the heat flow is mainly vertical and each heat source (dissipating element) can be seen as an independent thermal resistance to the heatsink. the thermal network can be roughly depicted as: figure 2. hsop20 simplified thermal model example assuming i v1 =100ma at v bat =16v, i v2 =150ma at v bat =16v (excluding can consumption). i can =50ma at v bat =16v, we have : p v1 =1.1w, p v2 =1.65w, p can =0.55w system assumptions: if t amb =85c and r thc/a =18c/w, this gives: t case =t amb +r th c/a x 3.3w = 85+18 x 3.3=145c and t j v1=t j v2=t jcan =155c. this example represents the limit for the maximum power dissipations with a hsop20. t ambient t case (heatsink) v1 power v2 power can power t j (max 155c) r thj/c =18c/w 6.5c/w 9c/w r thc/a (ecu supplier dependent) so28wb package the case(pin) to junction r th is here represented by only one thermal resistance for the total power since the 3 power sources strongly interact on the silicon for such a package. figure 3. so28wb simplified thermal model example assuming i v1 =45ma at v bat =16v, i v2 =45ma at v bat =16v (excluding can consumption). i can =50ma at v bat =16v, we have : p v1 =0.5w, p v2 =0.5w, p can =0.55w thus p total =1.55w system assumptions: if t amb =85c and r thc/a =25c/w, this gives: t case =t amb +r thc/a x 1.55w=85+25x1.55 =124c and t j v1=124 + 20 x 1.55= 155c. this example represents the limit for the maximum power dissipations with a so28wb. t case (pin) t j (max 155c) total power r thc/a t ambient r thj/c =20c/w MC33389 motorola 11 MC33389 device description introduction the system basis chip is an integrated circuit dedicated to car body applications. it includes three main blocks : - a dual voltage regulator - reset, watchdog, wake up inputs, cyclic wake up - can low speed fault tolerant physical interface supplies two low drop regulators and one switch to v bat are provided to supply the ecu microcontroller or peripherals, with independent control and monitoring through spi. voltage regulator v1 v1 is a 5v, 3% low drop voltage regulator dedicated to the microcontroller supply. it can deliver up to 100ma and is totally protected against short to ground (current limitation) and overtemperature. v1 is active in normal request, normal and standby modes. no forward parasitic diode exists from v1 to v bat .this means that, if v bat voltage drops below v1, no high current flowingfromv1tov bat will discharge the capacitor connected to v1. its stored energy will only be used to supply the microcontroller and gives time to save all relevant data. undervoltage reset v1 is monitored for undervoltage (power up, power down) and a reset is provided at rstb output for 1ms. this ensures proper initialization of the microcontroller at power-on or after supply is lost. on top of that, a flag is set in rsr register readable via the spi. overtemperature protection v1 internal ballast transistor is monitored for overtemperature. two detection thresholds are provided. a pre-warning threshold at 145c and a shut-off threshold at 175c. once the first threshold is reached, a flag is set in the otsr register. a maskable interrupt can be sent to the microcontroller. once the second threshold is reached, a flag is set in the otsr register, a maskable interrupt is sent to the microcontroller and v1 is switched off. once the junction temperature is back to the pre-warning threshold, v1 regulator it will be automatically switched on. table 4. v1 control note: current capability of v1, v2 and v3 depends upon the thermal management. over temperature shutdown might be reached and lead to turn off of v1, v2 and v3 for output current below their max current capability. conditions for v1 on conditions for v1 off normalrequest mode (at v1 power on) sleep mode (via spi) normal mode (via spi) shut-off temperature threshold reached standby mode (via spi) no v bat power supply (cold start) v1 below pre-warning temperature threshold emergency mode during reset voltage regulator v2 v2 is a 5v low drop voltage regulator dedicated to peripherals supply. it can deliver up to 200ma and is protected against short to ground (current limitation) and overtemperature. v2 is active in normal mode. undervoltage detection v2 is monitored for undervoltage and a flag is set in the vssr register. overtemperature protection v2 internal ballast transistor is monitored for overtemperature. two detection thresholds are provided. a pre-warning threshold at 140c and a shut-off threshold at 165c. once the first threshold is reached, a flag is set in the otsr register which is readable. a maskable interrupt can be sent to microcontroller. once the second threshold is reached, a flag is set in the otsr register, v2 is switched off. it can only be switched on again via the spi. table 5. v2 control switch v3 v3 is a 10 ? switch to v bat , it can be used to supply external contacts or relays. a great flexibility is given for the different possible ways for its control. it is protected against short to ground (current limitation). overtemperature protection v3 output transistor is monitored for overtemperature. once the threshold is reached, a flag is set in the vssr register, v3 is switched off. it will be automatically switched on once the junction temperature is back to the pre-warning threshold. table 6. v3 control conditions for v2 on conditions for v2 off normal mode (via spi) and v2 below shut off temperature threshold sleep mode, or standby mode or normalrequest or emergency mode (via spi) shut-off temp. threshold reached v1 disabled (for any reason) conditions for v3 on conditions for v3 off permanently in normal mode if configured via spi permanently in normal mode if configured permanently in standby mode if configured via spi normalrequest mode in sleep mode, during enable time of cyclic sense if configured permanently in standby mode if configured permanently in sleep mode if configured in sleep mode, during disable time of cyclic sense if configured overtemp threshold reached v1 disabled (for any reason) v2 over temperature shutdown MC33389 motorola 12 MC33389 device description supply and v bat block v bat monitoring v bat is the main power supply coming from the battery voltage after an external protection diode (for reverse battery). v bat is monitored for undervoltage and overvoltage. v bat undervoltage v bat is monitored for undervoltage, if it is below 4v the batfail flag is set in the vssr register and a maskable interrupt is sent to the microcontroller. v bat overvoltage when v bat is > 20v, the bathigh flag is set in the vssr register. a maskable interrupt is sent to the microcontroller. no specific action is taken to reduce current consumption (to limit power dissipation). this is to let the entire flexibility at the microcontroller for decision. can transceiver the device incorporates a low speed 125kbaud can physical interface. its electrical parameters for the canl, canh, rtl,rth,rx and tx pins are identical to the mc33388, standalone can physical interface. the mode control for the can transceiver (normal, v bat standby, sleep, etc...) are selectable through the MC33389 spi interface. baud rate up to 125kbit/s supports unshielded bus wires short-circuit proof to battery and ground in 12v powered systems supports single-wire transmission modes with ground offset voltages up to 1.5v automatic switching to single wire mode in case of bus failures automatic reset to differential mode if bus failure is removed low emi due to built in slope control and signal symmetry. fully integrated receiver filters thermally protected bus lines protected against automotive transients. low current busstandby mode with wake-up capability via the bus. an unpowered node does not disturb the bus lines. figure 7. can simplified block diagram termination protection rx tx can_h can_l rth rtl vdd2 spi transmitter receiver - fail detect - receive mode vdd2 vbat can transceiver register drivers can transceiver simplified block diagramm can transceiver description the can transceiver is an interface between can protocol controller and the physical bus. it is intended for low speed applications up to 125kbit/s in passenger cars. it provides differential transmission capability, but will switch in error condition to single wire transmitter and/or receiver. the rise and fall slopes are limited to reduce rfi. this allows use of an unshielded twisted pair or a parallel pair of wires for the bus. it supports transmission capability on either bus wire if one of the bus wire is corrupted. the logic failure detection automatically selects a suitable transmission mode. in normal operation (no wiring failures), the differential bus state is output to rx. the differential receiver inputs are connected to canh and canl through integrated filters. the filtered inputs signals are also used for the single wire receivers. the canh and canl receivers have threshold voltages that assure maximum noise margin in single wire modes. in the rxonly mode, the transmitter is disabled but the receive part of the transceiver remains active. in this mode, rx reports bus and tx activity (rx =tx or bus dominant). failure detection and management is the same as busnormal mode. failure detector the failure detector is active in rxtx and rxonly operation mode and detects the following single bus failures and switches to an appropriate mode. 1- canh wire interrupted 2- canl wire interrupted or shorted to 5v 3- canh short-circuited to battery 4- canl short-circuited to ground 5- canh short-circuited to ground 6- canl short-circuited to battery 7- canl mutually shorted to canh 8- canh to v2 (5v) note : shorts-circuit failures are detected for 0 to 50 ? shorts. MC33389 motorola 13 MC33389 device description the differential receiver (canh-canl) threshold is set at - 2.8v, this assures a proper reception in the normal operating modes. in case of failures 1, 2 and 5 the on-going message is not destroyed due to noise margin failures 3 and 6 are detected by comparators respectively connected to canh and canl. if the comparator threshold is exceeded for a certain time, the reception is switched to single wire mode. this time is needed to avoid false triggering by external rf fields. recovery from these failures is detected automatically after a certain time-out (filtering). failures 4 and 7 initially result in a permanent dominant level at rx. after a time out, the canl driver and the rtl pin are switched off, only a weak pull up at canl remains. reception continues by switching to single wire mode through canh. when the failures 4 or 7 are removed, the recessive bus levels are restored. if the differential voltage remains below the recessive threshold for a certain time, reception and transmission switch back to the differential mode. if any of the 8 wiring failure occurs, a flag is set in the tesrh and tesrl status registers. 8 different types of errors are distinguished out of these 8 errors and are separately stored in these register (see spi register description section on page 21). a maskable interrupt is sent to the microcontroller. on error recovery, the corresponding flag is reset after read-out operation. during all single wire transmissions, the emc performance (both immunity and emission) is worse than in differential mode. integrated receiver filters suppress any hf noise induced into the bus wires. the cut-off frequency of these filters is a compromise between propagation delay and hf suppression. in single wire mode, low frequency noise can not be distinguished from the wanted signal. in the event of a permanent dominant tx state (for more than 2ms) the output drivers are disabled. that assures the operation of the complete system in case of a permanent dominant tx state of one control unit. a defect control unit autonomous go to rxonly or termvcc mode. low power modes the transceiver provides a low power modes which can be entered and exit by a spi command. this is the busstandby mode with the lowest power consumption (for the transceiver). canl is biassed to the battery voltage via the rtl output and the pull-up current source on canl and pull- down current source on canh are disabled. wake-up requests are recognized by the transceiver, when a dominant state is detected on either bus lines (bus wake-up). on a bus wake-up request the sbc will activate the intb output or, if it is in sleep mode, switch to normalrequest mode. this event is stored in the wuisr status register. to prevent false wake-up due to transients or rf fields, wake-up threshold levels have to be maintained for a certain time. in the transceiver low power mode, failure detection circuit remains partly active to prevent increased power consumption in cases of error 3, 4,7 and 8. power on after the v bat supply is switched on, the sbc is in normalrequest mode. the corresponding mode for the can transceiver is busstandby. the can transceiver is supplied by v2. as long as v2 is below its undervoltage threshold, the transceiver is forced to busstandby mode (fail safe property). protection a current limiting circuit protects the transmitter output stages against short-circuit to positive and negative battery voltage. if the junction temperature exceeds a maximum value, the transmitter output stages are disabled. because the transmitter is responsible for a part of the power dissipation, this will result in a reduced power dissipation and hence a lower chip temperature. all other parts of the transceiver will remain operating. the canh and canl inputs are protected against electrical transients which may occur in an automotive environment. consequence of failure detections s1 is the switch from rth to ground s2 is the switch from rtl to v2 and s3 is the switch from rtl to v bat for each failure type is given which switch is open and which driver is disabled. failure 1 : nothing done failure 2 : nothing done failure3 : s1 open. driver canh is disabled failure4 : s2 and s3 open. driver canl is disabled failure5:nothingdone failure6 : s2 and s3 open. driver canl disabled failure7: s2 and s3 open. driver canl disabled failure8: s1 open. canh driver disabled can transceiver modes the can transceiver has its own functioning modes: rxtx mode, termvbat/termvcc mode, and rxonly mode. they are controlled by tcr register. rxtx mode full transmitting and receiving capabilities are enabled. full failure detection is enabled. note: standard/rxtx and extended/rxtx are equivalent. rxonly mode the transmitter is disabled but the receive part of the transceiver remains active. in this mode, rx reports bus and tx activity (rx =tx or bus dominant). note: standard/rxonly and extended/rxonly are equivalent. busstandby mode this is the low power mode for the can transceiver. the driver and receivers are disabled. wake-up capability on both bus lines as well as failure 3, 4, 7, 8 detection are enabled. in bus standby mode rtl termination is set to v bat . MC33389 motorola 14 MC33389 device description sbc modes global power save concept the sbc allows to minimize power consumption of the ecu. several operating modes are available to go to low power consumption when the full activity is not required. several possibilities are provided to wake-up the ecu. this allows to have peripherals or the microcontroller switched off when no activity on the ecu is required. two switchable independent supply voltages (v1 and v2) are provided for optimum ecu power management. generalities the sbc can be operated in four modes: sleep, standby, normal and emergency mode. after reset, the MC33389 is automatically initialised to a temporally mode, normalrequest, waiting for microcontroller configuration. reset mode this mode is entered after sbc power up, or if an incorrect software w/d trigger occurs. the minimum duration for reset mode is 1ms typical, and unless a v1 failure condition, the sbc enters the normalrequest mode after reset. in case of v1 failure condition leading to v1 low (ex: short to gnd), the sbc goes in reset mode. if v1 is still below reset threshold after 100ms, the behavior depends upon the device version a or c: - a version : the MC33389adw will enter sleep mode. - c version: the MC33389cdw and the MC33389cdh will stay in reset mode. normalrequest mode this is the default mode after MC33389 reset. v1 is active, v2 and v3 are passive. the sbc is not configured. the default values are set in the registers. the sbc is waiting for configuration data via the spi. if no spi data is received 75ms after the reset is released, then the sbc switches itself to sleep mode. the data the sbc must receive to consider that the microcontroller starts the configuration sequence is the sw timing word (in swcr register). once received this sw timing word, the watchdog timer becomes active. then any other control data can be sent from the microcontroller to sbc. the watchdog is not active in normalrequest mode before the sw timing word is programmed into the sbc. in this mode, neither v2 nor the can transmitter are active. table 8. normalrequest: v1 active, v2&v3 passive entering normalrequest leaving normalrequest sbc reset just released when firstly receiving the sw timing word, sbc goes to normal if time-out without receiving spi commands (75ms), sbc goes to sleep sbc normal mode in this mode, v1 and v2 are active, v3 can be set active or passive via the spi. therefore, the whole ecu can be operated. normal mode is entered by a swcr register configuration in normalrequest mode. table 9. sbc normal mode: v1 and v2 are active. v3 is active or passive sbc standby mode in this mode v1 is active, v2 is passive. v3 can be either permanently active or permanently passive. this is a low power mode with v1 active in order to have a fast reaction time in case of any wake-up. for standby mode, the sbc monitors the sw. it means the microcontroller runs and is monitored and must serve a watchdog trigger. table 10. standby: v1 active v2 passive, v3 active or passive, watchdog is active entering normal mode leaving normal mode by spi command by spi command, going to any other mode after swcr register configuration in normalrequest mode watchdog time out, going to normalrequest after activating reset v1 undervoltage detection, going to normalrequest mode after activating reset entering standby leaving standby if sw time-out going to normalrequest after microcontroller reset by spi command by spi command going to any other mode v1 undervoltage detection, going to normalrequest mode after activating reset external activation of the rstb pin MC33389 motorola 15 MC33389 device description sbc modes sbc sleep mode this is a low power consumption mode. v1 and v2 are disabled. v3 can be permanently disabled or cyclically active. table 11. sbc sleep mode: v1 and v2 are passive, v3 passive or cyclic. emergency mode in case the microcontroller detects the ecu or the system is not under control any more, it may decide to switch the sbc to the emergency mode. v1, v2, v3 will be passive and wake- up are not detected. the only way to leave this mode is to disconnect the ecu from the battery voltage (batfail detection). table 12. sbc emergency mode: v1 and v2 v3 are passive figure 13. typical behaviour at power on note: in normalrequest, if an spi command is received before the sw timing configuration (swcr register), it will not be taken into account by the sbc (except for the go to emergency mode). correspondence between sbc and can transceiver modes the table here below gives the different possible can transceiver modes versus sbc modes. entering sleep mode leaving sleep mode if sw timing not configured 75ms after entering normalrequest mode can wake-up, going to normalrequest by spi command if a wake-up is detected with cyclic sense for MC33389adw only: if v1 is below v1 reset for more than 100ms if a wake-up is detected with wake-up not connected to v3 (permanent sense) forced wake-up (see forced wake up section) spi wake-up (see wake up by spi section) entering emergency mode leaving emergency mode by spi command sbc batfail detection (dis- connection of the battery voltage) ecu connected to battery reset v1 low normalrequest sleep normal v1 on spi sw timing configuration at t<75ms no spi sw timing configuration at t=75ms (reset released) emergency spi go to emergency at t<75ms vbat > 4v and v1 low for t>100ms for MC33389adw only (a version) table 14. can modes versus sbc modes note: in case v2 is turned off either by spi command (standby mode) or by the sbc itself due to v2 over load condition (v2 short to gnd or v2 over temperature) the can is automatically set into the bus standby mode and does not return to txrx mode automatically when v2 is back to 5v. the can must be re configured to txrx or rxonly mode after a v2 turn off. watchdog general the software window watchdog function is used to monitors the microcontroller operation in normal and in standby modes. the window watchdog timing is derived from the sbc-clock. the desired watchdog timing must be first transmitted during the sbc configuration, in normalrequest mode, via spi to swcr register. it can also be changed later on. selectable watchdog timings are 5ms, 10ms, 20ms, 33ms, 50ms, 75ms, 100ms and 200ms. these timings correspond to the full disable window plus full enable window. figure 15. window watchdog timing as soon as the watchdog trigger is received in the enable window, the internal counter is reset and start a new disable window. the sbc triggers the watchdog word at csb low to high transition. any watchdog trigger outside the enable window leads to sbc reset. in normal and standby modes in normal mode the sbc get the watchdog word from the microcontroller via spi. in case of a trigger time failure (no trigger or trigger outside the enable window) the sbc-reset is switched to active. normalrequest, sleep and emergency mode watchdog is not active in this modes. when sbc is in the following mode can transceiver can be in reset condition bus standby mode normalrequest bus standby mode normal rxtx or rxonly or busstandby standby bus standby sleep bus standby emergency bus standby normal & v2 off (over load) (note) bus standby watchdog trigger sbc watchdog window earliest trigger time latest disabled window nom. trigger period time out latest sbc-reset out 50% 50% watchdog timing enable window reset trigger time time MC33389 motorola 16 MC33389 device description wake-up capabilities several wake up capabilities are available. forced wake-up the forced wake-up is enabled and disabled by spi in v3r register. it is used in sleep mode to automatically wake- up the system by supplying v1 with proper reset. this correspond to jump into normalrequest mode. if then, the sbc is not properly configured within 75ms, it switches back to sleep mode till the next wake-up. if both cyclic sense and forced wake-up are enabled by the spi in sleep mode, only cyclic sense will be active. the period of forced wake-up are 32ms, 64ms, 128ms, 256ms, 512ms, 1024ms, 2048ms, 8192ms, chosen by spi in cytcr register. wake-up inputs (local wake-up) / cyclic sense sbc provides 3 wake-up inputs to monitor external events such as closing/opening of switches. the wake-up feature is available in normal, standby and sleep modes. the switches can be directly connected to v bat or to v3. the sbc must be properly configured by setting bit wi2v3 in register v3r. in this case, wake-ups are only detected when v3 is on. it can take advantage of v3 cyclic sense feature. if both cyclic sense and forced wake-up are enabled by the spi in sleep mode, only cyclic sense will be active. options for wake input different conditions for wake-up can be chosen for wake- up input pins (via spi in wuicr register). no wake-up: no wake-up is detected, whatever occurs on wake-up inputs. high state: if the input pin voltage is above the detection thresholdduringmorethana20 s filter time, a wake-up is detected. a flag is set in the wuisr register. low state: if the input pin voltage is below the detection thresholdduringmorethana20 s filter time, a wake-up is detected. a flag is set in the wuisr register. change of state: each change of the wake-up input pin is considered as a wake-up, if it lasts more than a 20 sfilter time. the first reference state (no wake-up) is the wake-up input state when the sbc is programmed to this option. a flag is set in the wuisr register. multiple sampling events: when wake-up inputs are used with v3 in cyclic sense in sleep mode. for positive edge sensitivity, 2 samples low followed by 2 samples high are necessary to validate the wake-up condition. for negative edge sensitivity, 2 samples high followed by 2 samples low are necessary to validate the wake-up condition. for both edge sensitivity, 2 samples at a given state followed by 2 samples in the opposite state are necessary to validate the wake-up condition. wake-up inputs with cyclic sense connecting the external switches to v3 allows power saving since v3 can be programmed to be active, passive or cyclic (cyclic sense). this gives a great flexibility to reduce total power consumption while allowing full wake-up capabilities. cyclic sense is available only in sleep mode. the period of the cyclic sense can be chosen out of 8 different timings: 32ms, 64ms, 128ms, 256ms, 512ms, 1024ms, 2048ms, 8192ms programmable via spi in cytcr register. once activated, v3 remains ?on? during 400 s. the wake-up inputs states are sampled at 300 s. figure 16. v3 timing note: in sleep mode, the cyclic sense feature ?exclusive or? the forced wake-up is chosen (not both). figure 17. cyclic sense timing wake up inputs with permanent sense wake up detection can also be done on a permanent way in normal and standby mode. if the contacts are connected to v3, wake ups are only detected if v3 is on. wake ups are also detected on a permanent way in sleep mode if the contacts are directly connected to v bat (if they are connected to v3, only cyclic sense is available in sleep mode). local wake-up consequences in normal or standby modes, the real time state of each wake-up input pin is stored in the readable register wuirti. wake-ups are detected according to the option chosen. a flag is set in the wuisr register. a maskable interrupt is sent via intb output. in sleep mode, a local wake-up leads to a jump to normalrequest mode (via proper reset of the microcontroller). a flag is set in the wuisr register. 300us 400us v3 passive active cyclic sense programmable period wake-up inputs sample point 1 1 1 0 0 0 0 1 1 actual state (read) memory state intb (wake-up active=0) 0 80ms 160ms v3 wake-up switch status v(l1) read l1 intb (t0) (t1) open closed read setup 400 s 300 s sample point (80%) z o o m e d cyclic sense connected to wake-up inputs. example with wake-up input l1 sensitivity to low state and timing=80ms MC33389 motorola 17 MC33389 device description wake-up capabilities table 18. sbc mode versus local wake-up behaviour wake-up by spi in some applications, the microcontroller might be supplied by an external vdd and remains powered in sbc sleep mode. in this case, a feature is provided which makes possible to wake-up the sbc by spi activity. after v1 is totally switched off in sleep mode (v1<1.5v), if a falling edge occurs on csb (crossing 2.5v threshold), a wake-up by spi is detected, the sbc switches to normalrequest mode. a flag is set in isr2. sbc modes local wake-up behaviour normalrequest no detection normal and standby detection active according to the option. the event is stored in wuisr register.the sbc may activate intb output. real time state of each wake-up input pin available in wuirti register sleep detection active according to the option. the event is stored in wuisr register. the sbc switches to normalrequest mode emergency no detection interrupt output the intb output may be activated in the following cases: v bat overvoltage (bathigh) v bat undervoltage (batfail) hightemperatureonv1orv2 pre-warning temperature on v1 or v2 can bus failure spi error local wake-up (can be used for low battery detection) buswake-up all these interrupts are maskable (see register description section). rstb input/output the rstb (reset) pin is an input/output pin. the typical reset duration from sbc to microcontroller is 1ms. if longer times are required, an external capacitor can be used. sbc provides two rstb output pull-up currents. a typical 30 a pull up when vreset is below 2.5v and a 300ua pull up when reset voltage is higher than 2.5v. rstb is also an input for the sbc. it means the MC33389 is forced to normalrequest mode after rstb is released by the microcontroller general when normally working in two-wire operating mode, the can transmission can afford some ground shift between different nodes without trouble. nevertheless, in case of bus failure, the transceiver switches to single-wire operation, therefore working with less noise margin. the affordable ground shift is decreased in this case. the sbc is provided with a ground shift detection for diagnosis purpose. four ground shift levels are selectable and the detection is stored in the gslr register which is accessible via the spi. detection principle the gnd shift to detect is selected via the spi out of 4 different values (-0.7v, -1.2v, -1.7v, -2.2v). at each tx falling edge (end of recessive state) canh voltage is sensed. if it is detected to be below the selected gnd shift threshold, the bit shift is set at 1 in gslr register. no filter is implemented. required filtering for reliable detection should be done by software (e.g. several trials). gnd shift detection MC33389 motorola 18 MC33389 device description differences between MC33389adw and MC33389cdw and cdh in addition to the package there is a behavioural difference between the a and c version. in the a version: if in reset mode v1 stays below reset threshold for more than 100ms, the sbc automatically enters sleep mode. this could be the case if v1 is shorted or permanently over loaded, and going to sleep mode would then avoid system over current consumption. in the c version: if v1 is below reset threshold, the sbc enters and stays in reset mode (reset low) permanently. the table below summarizes the sbc operation modes. table 19. sbc operation mode figure 20. state machine mode v1 & v2 regula- tors, v3 switch wake up capabilities (if enabled) reset pin int software watchdog can cell reset state v1: on (unless failure condition v2: off v3: off low (duration 1ms) termvbat normal request v1: on (75ms time out) v2: off v3: off high. (active low -go to reset state- if v1 under voltage occurs) term vbat normal v1: on v2: on v3: on or off high. (active low -go to reset state- if w/ d or v1 under voltage occurs) if enabled, signal failure condition or l0/ l1/l2 inputs state change. running tx/rx, or rx only, or termvbat standby v1: on v2: off v3: on or off same as normal mode same as normal mode running termvbat sleep v1: off v2: off v3 off or cyclic -can - spi - l0,l1,l2 - cyclic sense - forced wake up low not active not running termvbat +wakeup capability emerge ncy v1: off v2: off v3 off none low not active not running termvbat MC33389 motorola 19 MC33389 device description powerdown reset normal request standby normal sleep reset counter (1ms) expired and v1 high (2) sbc power up v1 low (1) wa k eup(8 ) spi: standby (7) spi: normal (6) spi:sleep (5) sp i: sl e e p( 5 ) w / d: trigg e r(3) w/d: timeout (4) or v1 low (1) w/d: timeout (4) or v1 low (1) legend: 1: ?v1 low? means v1 below reset threshold 2: ?v1 high? means v1 above reset threshold 3: ?w/d: trigger? means scwr register write operation during normal request mode. 4: ?w/d: time out? means swcr register not written before w/d time out period expired, or w/d written in incorrect time window. in normal request mode time out is 75ms. 5: ?spi: sleep? means spi write command to mcr and mcvr registers, data sleep 6: ?spi: normal? means spi write command to mcr and mcvr registers, data normal 7: ?spi: standby? means spi write command to mcr and mcvr registers, data standby 8: ?wake up? means one of the following event occur: can wake up, forced wake, cyclic sense wake up, direct lx wake up or spi csb wake up. 9: ?v1 low > 100ms? means v1 below reset threshold for more than 100ms. 9a: this condition leads to sbc in sleep mode only for the MC33389adw (so28 package). 9b: v1 low for > 100ms does not lead to sleep mode for the MC33389cdw (so28wb package) and for the MC33389cdh (hsop20 package). 75ms time out expired (MC33389 a version only: v1 low > 100ms) (9) (9a) emergency spi: emergency spi: emergency MC33389 c version (9b) MC33389 motorola 20 MC33389 spi functionnal description general description the spi system is flexible enough to communicate directly with numerous standard peripherals and mcus available from motorola and other semiconductor manufacturers. spi reduces the number of pins necessary for input/output on the MC33389. the spi system of communication consists of the mcu transmitting, and in return, receiving one databit of information per clock cycle. databits of information are simultaneously transmitted by one pin, microcontroller out serial in (mosi), and received by another pin, microcontroller in serial out (miso), of the mcu. figure 21 below shows the basic spi configuration between an mcu and one MC33389. the spi serial operation is guaranteed to 2.0 mhz. figure 21. spi interface with microcontroller control and status reporting of the MC33389 the mcu is responsible for the control data transfer to the MC33389, while the MC33389 reports its status to the mcu. summarized below are the major data for control and status reporting. - spi initialization during start up - MC33389 control during operation - watchdog triggering - reading status registers of the MC33389 control data the control data are transferred from the mcu to the MC33389. a control word includes an address of a certain control register and the appropriate data. basically the following data will be transferred (see the spi register description section on page 21). - MC33389 mode control - supply control - forced wake-up timing - cyclic sense control - watchdog control - transceiver control status data the status data are transmitted from the MC33389 to the mcu. after receiving a valid register address from the mcu, the MC33389 returns the appropriate status. some of the major status data are listed below: - current operation mode status - wake-up sources - reset status - error status - overtemperature status - transceiver status mosi csb sclk miso mosi miso mc68hcxx MC33389 data transfer the data to and from the MC33389 are transferred in form of two bytes.the structure of the transferred information is the same for control the MC33389 and status reporting. the address field a5 to a0 (bit15 to bit10) contains the address of a control or status register in the MC33389. rw (bit9 and bit8) contains the read/write flag for the data field. the parity field is locatedatp3top0(bit7tobit4).thedatafieldd3tod0(bit3 to bit0) is attached to the 2 byte data word, see figure below. figure 22. the sbc is accessible via the spi interface in normalrequest mode, normal mode and standby mode. in all other modes (sleep mode, emergency mode), the voltage supply for the microcontroller in permanently switched off and the sbc input logic for miso, mosi, csb and sclk isn?t working (except spi wake-up function in sleep mode). writing data to write data in a spi register, two one-byte transmissions have to performed. the first byte contains the address of the register (msb first) and the read/write bits which have to be set to 1. the second byte contains the new data addressed by the previous byte (msb first) and the parity information. the calculation of the parity field p3-p0 has to follow the equations below: (ex-or) note, that during the transmission of the two bytes the csb pin remains 0. see figure23 hereafter. figure 23. the sbc sends back the old address, r/w, parity, and data information from a previous transmission. this data contains no useful information (e.g. status).it shouldn?t be used. in case of a wrong address field or parity mismatch, an interrupt will be issued and the sbc retains the old state. reading data to read data from a dedicated register two one-byte transmissions have to be performed. the first byte contains the address of the register (msb first) and the read/write flag setting to 0. the second byte needn?t to contain valid data, a5 a4 a3 a2 a1 a0 d3 d2 d1 d0 p3 p2 p1 p0 rw rw bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 address + r/w data parity mosi miso p3 d3 d0 = p2 d3 d2 = p1 d2 d1 = p0 d1 d0 = a5 a4 a3 a2 a1 a0 d3 d2 d1 d0 p3 p2 p1 p0 rw rw a3 a2 a1 a0 1 1 a5 a4 sbc spi data register bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hc08/12 spi data register old address + r/w old data old parity new address + r/w (1st byte) new data + parity (2nd byte) d3 d2 d1 d0 p3 p2 p1 p0 MC33389 motorola 21 MC33389 spi functionnal description nevertheless the parity calculation has to performed to avoid an interrupt caused by a parity mismatch. during a read operation the sbc sends back the old address and r/w bits and the new data addressed by the first transmitted byte starting with p3 after the last valid read/write bit has been received. note, that during the transmission of the two bytes the csb pin remains 0. figure below shows the content of the hc08/12 spi dataregister and the sbc spi data register before the transmission. the new address and r/w bits are already in the spi data register while the new data and parity bits are still in an appropriate microcontroller register or memory. this 2nd byte has to be loaded into the hc08/12 spi data register after the first byte has been transmitted to the sbc. figure 24. after transmission of the 1st byte the hc08/12 spi read buffer contains the old address and r/w bits received from the sbc. an appropriate operation in the microcontroller loads the new data and parity into the hc08/12 spi data register (2nd byte). in the sbc the internal logic loads p3-p0 and d3- d0 to the location of bit15 to bit8 in the sbc spi data register and will shift this data within the remaining eight clock cycles (figure below 25). figure 25. after sixteen clock cycles the microcontrollers read buffer contains the new parity and data and is now ready for the next transmission (see figure hereafter 26) a5 a4 a3 a2 a1 a0 d3 d2 d1 d0 p3 p2 p1 p0 rw rw a3 a2 a1 a0 0 0 a5 a4 000000 00 sbc spi data register bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hc08/12 spi data register old address + r/w old data old parity new address + r/w (1st byte) new data + parity (2nd byte) a5 a4 a3 a2 a1 a0 d3 d2 d1 d0 p3 p2 p1 p0 0 0 000000 00 sbc spi data register bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 hc08/12 spi data register new address + r/w new data new parity addressed by the new address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a3 a2 a1 a0 rw rw a5 a4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 old address + r/w in hc08/12 spi read buffer figure 26. . safety concept due the fact the spi interface is an on-board interface without any data fault detection capabilities, the spi interface of the MC33389 provides built-in fail save functions. address coding, based on increasing the hamming distance, parity check and generation for data. for the address and the read/write bits only codes with a hamming distance < 2 will be used. so, any single bit failure caused by disturbances will be recognized and handled. when one bit toggles in the address field during the transmission, no misbehaviour occurs. additionally, validation registers are implemented to validate safety critical settings in the MC33389, e.g. the mode control register mcr and its validation register mcvr. to change the appropriate settings, both registers must have the same content to switch to another mode. to increase data integrity a parity check is used. a parity module in the MC33389 ascertains the parity of the data field and compares the result with the received parity. when the parity check is successfully passed, data will be written into the addressed registers. the parity bits p3 to p0 results from the logic equations below: (ex-or) in case of error detection, the incoming data is not taken in the sbc and an error flag is set in an spi register. p1 p0 d3 d2 d1 d0 p3 p2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 new parity + new data in hc08/12 spi read buffer a5 a4 a3 a2 a1 a0 0 0 0 0 0000 rw rw a3 a2 a1 a0 0 0 a5 a4 sbc spi data register bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hc08/12 spi data register old address + r/w old data old parity p3 d3 d0 = p2 d3 d2 = p1 d2 d1 = p0 d1 d0 = MC33389 motorola 22 MC33389 spi functionnal description csb pin the system mcu selects the MC33389 to be communicated with, through the use of the csb pin. whenever the pin is in logic low state, data can be transferred from the mcu to the MC33389 and vice versa. clocked-in data from the mcu is transferred from the MC33389 shift register and latched into the addressed registers on the rising edge of the csb signal if the read/write bit is set and the parity check was successful. the csb pin controls the output driver of the serial output pin. whenever the csb pin goes to a logic low state, the miso pin output driver is enabled allowing information to be transferred from the MC33389 to the mcu. to avoid any spurious data, it is essential that the high-to-low transition of the csb signal occur only when sclk is in a logic low state. sclk pin the system clock pin (sclk) clocks the internal shift registers of the MC33389. the serial input pin (mosi) accepts data into the input shift register on the falling edge of the sclk signal while the serial output pin (miso) shifts data information out of the shift register on the rising edge of the sclk signal. false clocking of the shift register must be avoided to guarantee validity of data. it is essential that the sclk pin be in a logic low state whenever chip select bar pin (csb) makes any transition. for this reason, it is recommended though not necessary, that the sclk pin be kept in a low logic state as long as the device is not accessed (csb in logic high state). when csb is in a logic high state, any signal at the sclk and mosi pin is ignored and miso is tristated (high impedance). mosi pin this pin is for the input of serial instruction data. mosi information is read in on the falling edge of sclk. to program the MC33389 by setting appropriate programming registers, an sixteen bit serial stream of data is required to be entered the mosi pin starting with bit15, followed by bit14, bit13, etc., to bit0. for each fall of the sclk signal, with csb held in a logic low state, a databit is loaded into the shift register per the databit mosi state.the shift register is full after sixteen bits of information have been entered. miso pin the serial output (miso) pin is the tri-stateable output from the shift register. the miso pin remains in a high impedance state until the csb pin goes to a logic low state. the miso pin changes state on the rising edge of sclk and reads out on the falling edge of sclk. the mosi/miso shifting of data follows a first-in-first-out protocol with both input and output words transferring the msb first. module address map, the module address map is shown in table below. table 27. module address map address register register name $000 mode control register mcr $003 mode control validation registermcvr mcvr $005 v3 control register v3r $006 cyclic timing control register cytcr $009 software watchdog control register swcr $00a ground shift level register gslr $00c wake-up input control register wuicr $00f wake-up input status register wuisr $011 wake up input real time information wuirti $012 overtemperature status register otsr $014 transceiver error status register for canh tesrh $017 transceiver error status register for canl tesrl $018 reset source register rsr $01b voltage supply status register vssr $01d interrupt mask control register 1 imr1 $01e interrupt mask control register 2 imr2 $021 interrupt source register 1 isr1 $022 interrupt source register 2 isr2 $024 transceiver control register tcr MC33389 motorola 23 MC33389 spi registers description table 28. mcr ?mode control register mcr and mcvr registers are used to control the mode of the sbc. to change the operating mode of the sbc, both registers must have the same content. the order of writing the registers has to be taken into account. to set the sbc mode properly, mcr has to be written first then followed by mcvr write. a write operation sets the mcr and mcvr registers, a read operation perform a read out of the current status (msr - mode status register). the emergency mode is a regular mode. a reset of both mcr and mcvr registers occurs when rstb = low and the sbc is set to normalrequest mode. table 29. mcvr ? mode control validating register table 30. table 31. v3r ? v3r control register this register is used to configure the state of v3 high side switch in normal and standby modes, and the v3 operation and the forced wake up or the cyclic sense option for the sleep mode operation. table 32. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr $000 r msr2 msr1 msr0 w mcr2 mcr1 mcr0 reset 000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcvr $003 r msvr2 msvr1 msvr0 w mcr2 mcr1 mcr0 reset 000 mc(v)r2 mc(v)r1 mc(v)r0 msr2 msr1 msr0 automatically entered after reset normalrequest 0 0 0 001 normal 001 0 1 0 standby 0 1 0 100 sleep 100 111 emergency 111 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 v3r $005 r wi2v3 fwu cys v3r0 w reset 1000 wi2v3 fwu cys v3r0 comments x000 v3off only in normal and standby mode available x001 v3on xx1x cyclicsenseon x 1 0 x forced wake-up on only in sleep mode available MC33389 motorola 24 MC33389 spi registers description note: in low power modes cyclic sense has priority. a reset of the register occurs when rstb = low. table 33. cytcr ? cyclic timing control register this register is used to select the cyclic sense or force wake up timing. table 34. a reset of the register occurs when rstb = low table 35. swcr ? software watchdog control register this register is used to select the window watchdog time period. open window of the selected period is only the second half of the selected period. 1 x x x wake-up inputs linked to v3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cytcr $006 r cytcr2 cytcr1 cytcr0 w reset 000 cytcr2 cytcr1 cytcr0 comments t(ms) typical 0 0 0 timer on, t1 (default) 32 0 0 1 timer on, t2 64 0 1 0 timer on, t3 128 0 1 1 timer on, t4 256 1 0 0 timer on, t5 512 1 0 1 timer on, t6 1024 1 1 0 timer on, t7 2048 1 1 1 timer on, t8 8192 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 swcr $009 r swcr2 swcr1 swcr0 w reset 000 wi2v3 fwu cys v3r0 comments MC33389 motorola 25 MC33389 spi registers description table 36. the sw watchdog is only running in normal and standby mode. a reset of this register occurs when rstb = low table 37. gslr ? ground shift level register this register is used to monitor the ground shift of the vehicle network. r table 38. shift 1=ground shift above the threshold selected by gslr1 and gslr2. 0=no ground shift the shift information is latched until a read operation of the gslr register occurs. the gslr register is set to 0 after power on reset. a reset of gslr1 and gslr0 occurs when rstb = low. txdom 0=nofailureontx 1 = tx permanent dominant table 39. wuicr ? wake-up input control register/spi and bus wake-up status this register is used to configure the wake up level for the l0, l1 and l2 inputs. in read operation it reports the can wake up andspi(csb)wakeupevents . swcr2 swcr1 swcr0 comments t(ms) typical 0 0 0 timer on, t1 (default) 5 0 0 1 timer on, t2 10 0 1 0 timer on, t3 20 0 1 1 timer on, t4 33 1 0 0 timer on, t5 50 1 0 1 timer on, t6 75 110 timeron,t7 100 111 timeron,t8 200 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gslr $00a r txdom shift gslr1 gslr0 w reset 000 gslr1 gslr0 typ gnd shift level 000.7v 01-1.2v 10-1.7v 11-2.2v bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wuicr $00c r spiwu buswu wuicr1 wuicr0 w reset 0 0 0 0 MC33389 motorola 26 MC33389 spi registers description table 40. table 41. the information in spiwu and buswu is latched. bits spiwu and buswu will be reseted by a read operation of the wuicr register and are set to 0 after a power on reset. a reset of wuicr1 and wuicr0 occurs when rstb = low. table 42. wuisr ? wake-up input status register this register is used to read back the wake input (l0, l1 or l2) which has cause the sbc to wake up. table 43. in case of a wake-up event, the appropriate bit is set to 1. the bits will be reseted by a read operation of the register. after power on reset all bits are set to 0. table 44. wuirti ? wake-up input real-time information this register reports the real time information on the state (high or low) of the l0, l1 and l2 inputs. the bits wuirti2-0 contain the real time logic value coming from the wake-up inputs (0 mean input below threshold, 1 mean input above threshold. typical threshold is 3.5v). wuicr1 wuicr0 description comments 0 0 wake-up inputs disabled 0 1 positive edge sensitive 1 0 negative edge sensitive 1 1 positive and negative sensitive spiwu buswu description comments 0 0 no wake-up events x 1 wake-up event on can bus 1 x wake-up event on spi bus bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wuisr $00f r wuisr2 wuisr1 wuisr0 w reset 000 wuisr2 wuisr1 wuisr0 comments 0 0 0 no event on wake-up inputs x x 1 event on l0 x 1 x event on l1 1 x x event on l2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wuirti $011 r wuirti2 wuirti1 wuirti0 w reset MC33389 motorola 27 MC33389 spi registers description table 45. otsr ? overtemperature status register this register is used to read back the overtemperature status for the v1 and v2 regulators. in write mode, it is used to turn v2 on after a v2 over temperature shutdown has occurred. otv1: 1=v1 overtemperature shutdown, 0=v1 no overtemperature otv2: 1=v2 overtemperature shutdown, 0=v2 no overtemperature opwv1: 1=v1 overtemperature pre-warning, 0=v1 normal temperature opwv2: 1=v2 overtemperature pre-warning, 0=v2 normal temperature in case of v1 or v2 overtemperature the appropriate voltage regulators are switched off automatically and the overtemperature flags are set (latched). the flags can be reseted by a read operation of the register otsr. once v2 has been switched off because of overtemp (otv2=1) it can only be switched on again by forcing otv2c=0 by a write operation. the v1 and v2 pre-warning flags are set as long as the first overtemperature exists. the flags disappear, when the temperature is below the threshold. an overtemperature of the v2 power supply will also switch off v3. after a power on reset all bits of the register are set to 0. table 46. tesrh ? transceiver error status register for canh register used to report the can h failure status . table 47. in case of canh line failures, the appropriate bit(s) are set according to table 46. this information is latched. the register can be reseted by a read operation. after power on reset, all bits are set to 0. table 48. tesrl ? transceiver error status register for canl and tx register used to report the canl and tx permanent dominant failure status . bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 otsr $012 r opwv2 opwv1 otv2 otv1 w otv2c reset 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tesrh $014 r tesrh3 tesrh2 tesrh1 tesrh0 w reset 0 0 0 0 tesrh3 tesrh2 tesrh1 tesrh0 0000 nofailureoncanh 0 x 0 1 canh wire interruption x x 1 x canh short circuited to v bat 0 1 0 x canh short circuited to ground 1 x 0 x canh short circuited to v cc bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tesrl $017 r tesrl3 tesrl2 tesrl1 tesrl0 w reset 0 0 0 0 MC33389 motorola 28 MC33389 spi registers description table 49. in case of canl line failures, the appropriate bit(s) are set according to table 48. this information is latched and the register can be reseted by a read operation. after power on reset, all bits are set to 0. table 50. rsr ? reset source register this register reports the source of a reset that has occurred . rsr0: 1 => vdd1 undervoltage occurred (rsr2=1 in this case), 0=> no undervoltage on vdd1 occurred rsr1: 1 =>sw watchdog reset occurred (rsr2=1 in this case), 0=>no sw watchdog reset occurred rsr2: 1 =>external reset occurred (rsr0=rsr1=0 in this case), 0=>no external reset occurred events related to the bits in register rsr are latched. all bits can be reseted by a read operation of the register. after a power on reset, rsr2 and rsr0 are set to 1. therefore the first read out of the register after power on delivers rsr[2:0] = [101]. table 51. vssr ? voltage supply status register register used to monitor the status of the v2, v3 and vbat voltage level. table 52. v2sr: 1=v2 on, 0=v2 off v3sr: 1=v3 overtemperature, 0=v3 no overtemperature vbsr1 is a real time information and cannot be reseted. bits v3sr, v2sr and vbsr0 are latched and can be reseted by a read operation of the register. tesrl3 tesrl2 tesrl1 tesrl0 0000 nofailure 0 x 0 1 canl wire interruption 010x canl short circuited to ground/ canh mutually shorted to canl x x 1 x canl short circuited to v bat 1 x 0 x canl short circuited to vdd bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsr $018 r rsr2 rsr1 rsr0 w reset 101 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vssr $01b r v3sr v2sr vbsr1 vbsr0 w reset 0 0 por 0 0 0 1 vbsr1 vbsr0 0 0 no failure on v bat x 1 undervoltage (batfail) 1 x overvoltage (bathigh) MC33389 motorola 29 MC33389 spi registers description table 53. imr1 ? interrupt mask control regis the next two registers (imr1 and imr2) are used to mask the interrupt function. table 54. imr2 ? interrupt mask control register 2 to enable the appropriate interrupt, the mask bit has to be set to 1. for disabling the interrupt the bit must be cleared to 0. after a power on reset or rstb = low, the bits are cleared to 0. all interrupts are disabled. explanation for the abbreviations: hv : v bat high voltage ht:hightemperatureonv1orv2 mtpw : medium temperature pre-warning on v1 or v2 batu: battery undervoltage (batfail) busf : can bus failure spie : spi error wu : wake-up table 55. isr1 ? interrupt source register the next two registers (isr1 and isr2) are used to read the interrupt source. table 56. isr2 ? interrupt source register 2 all bits in registers isr1 and isr2 are copies of the appropriate bits in different spi registers. for a faster read out, these bits are merged in isr1 and isr2. a reset cannot be done for registers isr1 and isr2. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 imr1 $01d r hv htpw mtpw batu w reset 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 imr2 $01e r busf spie wu w reset 000 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 isr $021 r hv htpw mtpw batu w reset 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 isr $022 r busf spie wu w reset 000 MC33389 motorola 30 MC33389 spi registers description table 57. tcr?transceiver control/status register this register is used to control the state of the can transceiver (can transceiver state is also dependant upon the sbc mode). when it is read, this register reports the can transceiver state and a can overtemperature condition . table 58. tot 1 => transceiver overtemperature 0 => normal temperature the mode bit selects between the standard and extended physical layer mode. any conditions forcing the transceiver to termvbat lead to reset of tcr0 tcr1 bits. after power on reset all bits of the register are set to 0. the information tot is latched. to reset tot a read operation of tcr has to be performed. in case of rstb = low the register content remains unchanged. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcr $024 r tot tsr2 tsr1 tsr0 w tcr2 tcr1 tcr0 reset 0 0 0 0 tcr2 tcr1 tcr0 tsr2 tsr1 tsr0 0 0 0 standard/termv bat 000 1 0 standard/rxonly 0 1 0 1 1 standard/rxtx 0 1 1 MC33389 motorola 31 m c33389 application sleep mode activation once in sleep mode, the sbc turns off v1 and v2 regulator. thus the micro controller can not run any mode. in order to have it run again, the sbc should enable and turn on v1, and this is achieve by an sbc wake up event. several options are available to wake up the sbc and the application and have the micro controller in run mode. some wake up are selectable, some are always active in sleep mode. - wake up from can interface and wake up from spi (csb) are always active. - wake up from l0/l1/l2 inputs, with and without cyclic sense and the fwu (forced wake up) are selectable. the selection must be done while the sbc is in normal or standby mode, and prior to enter sleep mode. general condition to enter sleep mode in order to make sure the sbc enters the sleep mode, and in addition to the write into mcr and mcvr register, all previous wake up conditions must have been cleared. to clear a wake up condition requires that the appropriate register is read. after an sbc power up from ?zero? (batterypoweruporcold start), the following registers must be read: - wuicr: possible wake up event report from can bus - rsr: report a v1 undervoltage - vssr: reports a vbat fail flag once these read operation are done, the wake up conditions or flag are reset. the vssr register bit vbsr0 can be used to determined if the sbc has experience a loss of battery voltage. after an sbc wake up from ?sleep mode? the following registers indicate the wake up source and must be cleared in order to allow the sbc to enter sleep mode again: - wuicr: wake up event report for can or spi buses. - wuisr: wake up event report for the l0/l1/l2 inputs. - rsr: report a v1 undervoltage - vssr: reports a vbat fail flag -etc the paragraphs below describe the write operation to be done for the several sleep mode and wake up control options. in addition to fwu, cyclic sense and direct wake up, the can and spi wake will always be activated. sleep mode with can and spi wake up the enter sleep mode and activate the only the can or spi wake up, no dedicated wake up condition must be done. in sleep mode the sbc has can and spi wake up always active. to enter sleep mode in this case, while the sbc is in normal or standby mode: - write to v3r register: data 0000 (this clear the bit wi2v3 whichissetto1afterreset). - write to mcr register: data sleep (100) - write to mcvr register: data sleep (100) the sbc then enters sleep mode. sleep mode enter with forced wake up to enter sleep mode and activate the forced wake up the following register must be written: - write to v3r register, data 0100), this set the fwu bit to 1. - write to cytcr register the desired wake up time. (this sets the time the sbc will stay in sleep mode). - write to mcr register: data sleep (100) - write to mcvr register: data sleep (100) the sbc then enters sleep mode. it will wake up after the time period selected in the cytcr register. sleep mode enter with cyclic sense to enter sleep mode and activate the cyclic sense wake up the following register must be written: - write to v3r register, data 1010, this set the vi2v3 and cys bits to 1. - write to cytcr register the desired cyclic sense period. (this sets the time the sbc will wait in sleep mode to turn on v3 and sense the lx inputs). - write to wuicr bits 0 and 1 to select the edge sensitivity for the lx inputs. - write to mcr register: data sleep (100) - write to mcvr register: data sleep (100) the sbc then enters sleep mode. it will periodically turn on v3 and while v3 is on, sample the level of the ls inputs. if any of the 3 lx inputs is in the correct state for two consecutive samples, sbc will wake up. if not, it will stay in sleep mode. (refer to device description for detail). sleep mode enter with direct lx input wake up to enter sleep mode and activate the direct wake up from the lx inputs, the following register must be written: - write to v3r register, data 0000), this clear vi2v3 bit. - write to wuicr bits 0 and 1 to select the edge sensitivity for the lx inputs. - write to mcr register: data sleep (100) - write to mcvr register: data sleep (100) the sbc then enters sleep mode. it will wake up as soon as any of the lx input read the correct state. figure 59. typical sleep current vs temp and batt voltage 40 100 60 120 80 140 typ sleep current (ua) 16v temperature (c) -50 0 50 100 150 -2525 75125 160 180 12v 6v MC33389 motorola 32 MC33389 application figure 60. typical application schematic 1 v1 vbat v2 reset int csb miso mosi sck tx rx canh canl rtl rth v3 l0 l1 l2 c3 c4 c5 c6 c1 c2 rp0 rl rh gnd gnd can spi vdd int reset auxillary 5v auxillary 12v s0 rs0 cl0 rp1 s1 rs1 cl1 rp2 s2 rs2 cl2 ignition can bus c1: 22uf c2: 100nf c3: 22uf, esr < c4: 100nf c5: 22uf, esr < c6: 100nf rh> 500 ohms rl> 500 ohms rp0,1,2: 22k rs0,1,2: 22 k cl0,1,2: 10nf (v3 supplies switch pull up resistors. sleep mode with cyclic sense). figure 61. typical application schematic 2 (v3 supplies local switch 12v. vbat v3 l0 l1 l2 c1 c2 rp0 gnd auxillary local 12v s0 rs0 cl0 rp1 s1 rs1 cl1 rp2 s2 rs2 cl2 ignition switch switch pull up resistors supplied sleep mode without cyclic sense). from switch battery line. figure 62. reset duration extension v1 reset c3 c4 vdd reset MC33389 cr micro figure 63. typical application schematic (wake up input linked to peripheral circuits: (ex: low speed can or lin transceivers). v1 vbat v2 reset int csb miso mosi sck tx rx canh canl rtl rth v3 l0 l1 l2 c5 c6 c1 c2 rp0 rl rh gnd gnd can 1 spi vdd int reset auxillary 5v auxillary 12v s0 rs0 cl0 ignition can bus # 1 canh canl rtl rth rl rh can bus # 2 gnd inh mc33388 lin 1k lin bus gnd inh mc33399 +12v vbat vdd vsup can 2 sci spi bus tx/rx tx/rx MC33389 motorola 33 MC33389 application software and debug of application using the MC33389 the sbc offers several capabilities to help user debug its application. - external bias of v1 and reset pin. - turn off of the software watchdog in standby mode. - special debug samples with software watchdog disable at power up (contact local motorola representative). debug and program download into flash memory while the sbc is powered it enters normal request and expect within the 75ms time period of the nr mode an spi tigger word (to enter normal mode and select the w/d time period). if this does not occurs, the sbc enter sleep mode and turn off v1. when the software is been debug, and when using development tools, it is not always easy to make sure these events properly. it is thus possible to externally power the v1 line with an external 5v supply, and to force the reset pin to v1 or to and external 5v. these can be done at nominal voltage and temperature. by doing this, 5v is provided to the mcu vdd and reset lines. under this condition the sbc is not operational. however the reset pin is pulled low and is sinking 5ma to ground. this means that the external circuitry which drive reset must have a current capability higher than 5ma in order to drive the reset in high state. disable of software watchdog in standby mode the software watchdog can be disable in standby mode only. in order to disable it the following operation must be done: - write to mcr register: data 011 (bit 2, bit 1, bit 0) - write to mcvr register: data 011 (bit 2, bit 1, bit 0) then the sbc enters the standby mode without software watchdog. however the v2 can not be turn on, and the can cell can not be used. special device special components are available to make the debug even easier. these device has a special behaviour which at power up disable the watchdog. these device can be available through marketing only. contact local motorola representative for more detail. the behaviour of such special parts is as follow: - at power up (from vbat =0v), the sbc enters "normal request mode" and stays in this mode permanently. v1 is on, v2 and v3 off, can in term vbat. for reference, with MC33389adw and MC33389cdh units it stays there 75ms only and go to sleep if no spi. - to get the sbc out on normalrequest mode, write to swcr register any valid data. this will enable the sbc to enter normal mode, with v1 and v2 on. once this is done, the sbc is controllable through spi, in the same way as the normal versions. it can be turned in sleep. after wake up it enters nr mode (same as after power up described above). only difference is that there is no need to refresh the software watchdog. internally, the watchdog is running but when time out elapsed a reset is not generated. when application debug is advanced enough, it is possible to enable the w/d-reset function. to re activated the w/d effect, the vssr register, bit vbsr0 (bat fail) must be read (cleared). when this is done, the w/d and 75ms timer of the nr mode effects are activated. however, due to re synchronisation, it is likely that at some point a reset is generated and that the sbc enter reset state then normalrequest mode. when the sbc has had it w/d reactivated it is not possible to deactivated it again by software. the only way to do this is to remove battery supply voltage (vbat < 3v for more than 200us) and then power up the sbc. MC33389 motorola 34 MC33389 case 979c ? 02 issue a seating plane datum plane bottom view a x 45 e1 e d h e 18x b m bbb c 20 11 10 1 e2 notes: 1. controlling dimension: millimeter. 2. dimensions and tolerances per asme y14.5m, 1994. 3. datum plane ? h ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. dimensions d and e1 do not include mold protrusion. allowable protrusion is 0.150 per side. dimensions d and e1 do include mold mismatch and are determined at datum plane ? h ? . 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the b dimension at maximum material condition. 6. datums ? a ? and ? b ? to be determined at datum plane ? h ? . 7. dimension d does not include tiebar protrusions. allowable tiebar protrusions are 0.150 per side. d2 d1 e3 ??? ??? a2 section w ? w b c1 b1 c e4 a m aaa c exposed heatsink area a b c h pin one id 10x y gauge plane detail y (1.600) l w w bbb c l1 a1 a3 dim min max millimeters a 3.000 3.400 a1 0.100 0.300 a2 2.900 3.100 a3 0.00 0.100 d 15.800 16.000 d1 11.700 12.600 d2 0.900 1.100 e 13.950 14.450 e1 10.900 11.100 e2 2.500 2.700 e3 6.400 7.200 e4 2.700 2.900 l 0.840 1.100 l1 0.350 bsc b 0.400 0.520 b1 0.400 0.482 c 0.230 0.320 c1 0.230 0.280 e 1.270 bsc h ??? 1.100 0 8 aaa 0.200 bbb 0.100 e/2 case outline MC33389 how to reach us: usa / europe / locations not listed : motorola literature distribution; japan : motorola japan ltd.; sps, technical information center, 3-20-1, p.o. box 5405, denver, colorado 80217. 1-303-675-2140 or 1-800-441-2447 minami-azabu, minato-ku, tokyo 106-8573 japan. 81-3-344-3569 technical information center: 1-800-521-6274 asia / pacific : motorola semiconductors h.k. ltd.; silicon harbour centre, 2, dai king street, tai po industrial estate, tai po, n.t., hong kong. 852-26668334 home page : http://www.motorola.com/semiconductors motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of a ny product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ? typical ? parameters can and do vary in different applications and actual performance may vary over time. all operating parameters, including ? typicals ? , must be validated for each customer application by customer ? s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to sup port or sustain life, or for any other appl ication in which the failure of the motorola product could create a situation where personal injury or death may occu r. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attor ney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are the property of their respective owners. ? motorola, inc. 2002 a1 case 751f ? 05 issue f 1 15 14 28 b s a m 0.025 b s c m 0.25 b m seating plane a notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimensions d and e do not include mold protrusions. 4. maximum mold protrusion 0.015 per side. 5. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.13 total in excess of b dimension at maximum material condition. dim min max millimeters a 2.35 2.65 a1 0.13 0.29 b 0.35 0.49 c 0.23 0.32 d 17.80 18.05 e 7.40 7.60 e 1.27 bsc h 10.05 10.55 l 0.41 0.90 0 8 l c pin 1 ident a b d e h e 0.10 c c a s e outline |
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